PDF ↗
Home/Primer/Why compute qualification is the hard problem
Section 3

Why compute qualification is the hard problem

Three reasons the hard half does not scale the way the easy half does.

1. The test for success is a test you hope never happens

A newly assembled server's success criterion is a burn-in test you run today. A power-delivery or thermal design's success criterion is the absence of a failure that would only show up after weeks or months of sustained 100kW-plus load — a hot spot that shortens a GPU's working life, a coolant-loop design that cannot hold its target temperature once every rack in a hall is running flat out simultaneously. You cannot inspect your way to confidence here; only running the system hard, for a long time, tells you whether the engineering was actually sound.

2. Re-qualification, not one-time qualification

NVQual certification is not a one-time badge. Nvidia's architecture cadence — Hopper, then Blackwell, now Vera Rubin, roughly annually — means a manufacturing partner has to re-certify its system design against an entirely new reference specification on almost every cycle. There is no equivalent of "the line still builds the same rack it did two years ago" in this industry; each generation is close to a fresh qualification exercise, on a timetable set by Nvidia's own product roadmap, not the manufacturer's.

3. The gatekeeper is also the rationer

Unlike a conventional supplier-qualification programme, here the party that certifies your design is the same party that decides whether you get the chips to build with it at all — and that same party is reported to be actively narrowing the field. Nvidia's own shift toward "customisation not allowed" components (§1) and its reported move to centralise assembly of its newest rack designs among a smaller circle of manufacturers means the qualification bar and the allocation bar are rising together. A company that qualified successfully on one generation has no guarantee the next generation leaves it the same room to add value, independent of anything it does right.

The chip and memory layer keeps the margin; the box-builder keeps the volume. Reported gross/operating margins, 2025-26 disclosures, and reported white-box assembly margin compression — see Notes for the individual sources behind each bar.
Educational material only — not investment advice. Dart Consultants is not a SEBI-registered Investment Adviser or Research Analyst.