Every good version of this kind of report is built on one real structural asymmetry inside the product. Here is the AI compute stack's.
Taking a chassis, a set of GPU boards, power supplies and cabling, and assembling them into a server or rack according to Nvidia's own MGX or HGX specification, is a capital-and-process scaling problem. Buy the assembly line and the test bench; hire and train technicians; run the burn-in test the specification calls for. Any competent electronics-manufacturing-services (EMS) operation can, in principle, attempt this — the underlying skills are the same ones India built up over two decades of mobile-phone and consumer-electronics contract manufacturing, not invented for this report. Failure here is visible and immediate: a board either boots and passes burn-in, or it does not.
The same rack, run at the 120-132 kilowatts a modern GB200 NVL72 configuration draws under sustained load, is a thermal, electrical and documentation problem with two layers India engages very differently. The first layer — the chip itself, fabricated on a leading-edge node and joined to its high-bandwidth memory through TSMC's CoWoS advanced-packaging process — sits almost entirely outside India today; that packaging capacity is reported "sold out through 2026" globally, regardless of anything an Indian company does. The second layer — the power-delivery network and liquid-cooling loop that keep the chips already inside the rack from throttling or failing — is one India's listed companies can and do engage with, but even here Nvidia's own reference designs are steadily narrowing the room for anyone else's engineering to matter (§1). Both layers share the same failure signature: invisible and delayed. A marginal power-delivery design does not fail on a bench test; it fails as GPU throttling or outright hardware failure after weeks of sustained real-world load, exactly when it is most expensive to discover.
| The easy half — the box | The hard half — the compute | |
|---|---|---|
| What it is | Assembling a chassis, boards, PSUs and cabling to Nvidia's own reference design | The chip/packaging/memory layer (outside India) plus the power-and-thermal engineering that keeps a dense rack alive (partially inside India) |
| Certification gate | Passing burn-in against the reference-design test plan | NVQual system-level stress testing, repeated every architecture generation |
| How it fails | Visible immediately — the board does not boot or pass burn-in | Invisible and delayed — throttling or failure emerges only after sustained real-world load |
| Who can attempt it | Any well-capitalised EMS operation | A much smaller population with real thermal/power engineering depth, and it is Nvidia, not the market, that ultimately decides who gets the chips to try |
| Where the margin sits | Thin, and compressing further — see §9's margin data | Thick at the chip and memory layer (Nvidia, SK Hynix, Micron); thinner but real at the India- accessible packaging and design-services layers — see §5 |
The box is the easy part. The chip allocation, and the engineering that keeps the chip alive once it is in the box, is the product. Everything else in this report — the value ladder in §5, the margin data in §9, the ratings in §11 — is really a question of how much of a given company's revenue sits on the allocation-and-engineering side of this line, versus the box-building side.
